Design of Serial Bus Chip Test Experiment Platform Based on AT89C51 MCU

When using the serial interface chip to expand the system, after initially selecting the serial interface chip, in order to better understand the resources of the chip, developers usually build a simple hardware circuit and compile corresponding software before the system design. The final design scheme is determined after the performance is verified. According to this need, this paper designs an experimental platform for serial bus chip testing.

Authors: Xia Jiqiang, Xing Chunxiang, Lu Mingzhen, Man Qingfeng

When using the serial interface chip to expand the system, after initially selecting the serial interface chip, in order to better understand the resources of the chip, developers usually build a simple hardware circuit and compile corresponding software before the system design. The final design scheme is determined after the performance is verified. According to this need, this paper designs an experimental platform for serial bus chip testing. The platform uses a PC as the man-machine interface, and uses a single-chip microcomputer to generate the serial communication sequence of the chip. The application of this platform can greatly simplify the testing process before the chip is used. This platform also provides a quick learning tool for beginners of serial expansion of single-chip microcomputers. This platform currently integrates four serial devices: SPI, One-wire, Microware and I2C. In the future use, the types of serial interfaces can be increased as needed.

1 Structure of Serial Expansion Platform

The core of the lower computer is the AT89C51 single-chip microcomputer. The single-chip microcomputer itself does not have SPI, One-wire, Microware, and I2C interfaces. It uses the virtual device technology and adopts the modular design idea in the single-chip microcomputer to solidify the serial access subroutines of the four interfaces, which are called by software. To complete the sequence of these serial expansions, use the ordinary I/O port line of the microcontroller to simulate four serial interfaces, and leave a large general board space on the lower computer circuit board or use a standard connector to connect the serial interface. The interface is drawn out, which is convenient to connect with the chip to be tested. The AT89C51 single-chip microcomputer does not have an RS-232 interface, but its UART port can use a chip such as MAX232 to expand a simple RS-232 interface, which is connected to the RS-232 interface of the host computer. The lower computer The structure is shown in Figure 1.

During the test, connect the chip to be tested with the corresponding serial interface, and the operator sends the access command and data to the lower computer through the RS-232 interface on the upper computer; after analyzing it, the lower MCU calls the corresponding timing simulation program to access the waiting computer. Test the chip, upload the results to the host computer through the RS-232 interface, and Display it on the host computer. From the perspective of the entire test process, as long as you care about the input and output of commands and data, you don’t need to care about the specific timing, which is similar to a transparent operation. After the test, the subroutines in the single-chip microcomputer can be transplanted into the actual application software by slightly cutting them, which provides convenience for development. The implementation of these four serial communication interfaces will be introduced separately below.

2 Implementation of Four Serial Communication Interfaces

In serial expansion, it can be divided into single-master system and multi-master system according to the number of interface masters. Among them, single-master system is the most common application. In single-master system, there is one master control device and multiple slaves device, the transmission of data is controlled by the master device. The master device starts and stops the transmission of data and provides a synchronous clock signal. The most versatile slave devices are used in applications. The serial expansion platform in this article is mainly aimed at these slave devices. Design. Therefore, the platform adopts a single-master device system structure, and only considers the use of the general-purpose I/O port line of the microcontroller to simulate the sequential logic of the master device accessing the slave device.

2.1 I2C bus interface timing

The I2C serial bus is an on-board inter-chip serial bus proposed by Philips. It can easily realize the expansion of peripheral devices with two wires. Figure 2 shows the basic read and write timing of the master device to the slave device. , SDA is the data line, and SCL is the clock line.

The basic unit of data transmission on the I2C bus is a byte, which adopts the low-order first format. The data transmitted between the master and slave devices at a time is called a frame, which consists of a start signal, several data bytes, a response bit, and a stop signal. It can be seen that the main commands of I2C are only read and write. Although the bytes read and written are different according to the specific device, the timing relationship will not change. According to this, the lower computer only needs to have the basic I2C. The timing sequence is enough. These basic timing sequences include: start, write byte, read byte, acknowledge bit, stop signal, and can be combined into two subroutines: read N-byte subroutine, write N-byte subroutine.

2.2 Serial peripheral interface SPI

SPI (Synchronous Serial Peripheral Interface) was proposed by Motorola. It is a three-wire synchronous interface, which is synchronous signal, input signal and output signal. In addition, each expansion chip also needs a chip select line, and the main device passes the chip The select line strobes the slave device with which it communicates. Figure 3 shows the timing diagram of the SPI. Among them, SCK is the synchronous clock pulse, SS is the chip select line, MOSI is the data output line of the master device and the data input line of the slave device, MISO It is the data input line of the master device and the data output line of the slave device.

SPI is full-duplex, that is, data can be sent and received at the same time. If only data is written to the slave device, the master device can discard the data read at the same time; conversely, if only data is read, it can be written after the command byte. Arbitrary data can be input. The data transfer is in bytes and adopts the format of high-order first. The communication program of the SPI interface can be simplified as: writing and reading N-byte subroutines.

2.3 Microware serial communication interface

NS’s Microware is a serial synchronous duplex communication interface, which consists of a data output line, a data input line and a clock line. The clock lines of all slave devices are connected to the same SK line, and the master device communicates to the SK line. The data output line DI of the master device is connected to the data input lines of all slave devices, and the data output lines of the slave devices are connected to the data of the master device. On the input line DO. Similar to the SPI interface, each slave device also needs to provide an additional chip strobe line CS (note: it adopts a high strobe mode). Figure 4 shows the basic timing sequence of the master device to the slave device operation , including write start bit, write operation code and read byte, data exchange adopts high order first format. Figure 4 shows the situation when two bytes are read, after the master device finishes writing the start bit and operation code After that, the slave device will respond with a “0”. This acknowledge bit is given when the master device has written the last bit of the opcode. In this paper, the master device is slow and can not consider waiting for this bit. The general purpose of the Microware interface Subroutines include: start subroutine, read N-byte subroutine, and write N-byte subroutine. Different Microware devices support different start bits and opcodes, but they can be artificially composed of appropriate bytes.

2.4 One-wire bus

One-wire bus is a protocol developed by DALLAS company. It consists of a bus master node and one or more slave nodes. It reads data from the slave chip through a signal line. Each one conforms to One-wire The slave chips of the protocol have a unique address, including a 48-bit serial number, an 8-bit family code and an 8-bit CRC code. The master chip addresses each slave chip according to the 64-bit difference. One- The wire bus uses one wire to realize two-way communication. Therefore, its protocol has strict requirements on timing. For example, the timing of response has clear time requirements. The basic timing includes reset and response timing, write one bit timing, read one bit timing, As shown in Figure 5 and Figure 6. In the reset and response sequence, after the master device sends a reset signal, the slave device is required to send back the response signal within a specified time; in the bit read and bit write sequence, the master device must be in the specified time. The data is read back or written out within the time limit. In order to be as consistent as possible with other subroutines of the analog interface in terms of structure and form, the bit read and bit write sequences are extended in the One-wire simulation sequence program to form the lower byte first. The timing of reading and writing, the timing of writing one byte is shown in Figure 7. Finally, three subroutines are formed: reset and response subroutine, write N bytes subroutine and read N bytes subroutine.

2.5 Lower computer software

Functionally, the function of the lower computer software is to receive the commands issued by the upper computer, analyze the commands, and combine and call the sequence subroutines according to the commands to form the correct access sequence logic; if there is return data, return the data. Send back to the host computer for display. The analog sequence subroutines of the four serial interfaces have been briefly introduced before. Due to space limitations, each subroutine cannot be described in detail. For further sequence descriptions, you can refer to the relevant references and Related manuals. Only the overall software flow of the lower computer is given here, as shown in Figure 8. The commands related to the upper computer are introduced in the protocol of the communication between the upper computer and it.

3 Realization of the host computer communication software

As a human-computer interaction interface, the upper PC is responsible for sending the manually analyzed data bytes to the lower computer, which provides developers with transparent operations on the chip. That is, when operating a certain type of chip, they do not care about the specific intermediate details. In the process, it is only necessary to analyze the data, form the corresponding data frame, and send it to the lower computer to complete the operation of the chip. The upper computer divides the operating chips into four categories (I2C, SPI, Microware, One-wire), using a word Sections are identified (0, 1, 2, 3). If only the write operation is performed, the upper computer will not operate after sending the write byte; if the read operation is performed, the sent byte needs to be reset and wait for the lower computer. The returned data byte. In Microware and One-wire protocols, the place where the start bit or reset signal must be sent can be identified by a special byte. The data frame sent by the upper computer to the lower computer is determined by the start byte and the communication selected word. Section, read/write command byte, number of bytes and data bytes. Figure 9 shows the composition of the data frame sent by the upper computer and the data frame returned by the lower computer in the two cases of reading and writing.

concluding remarks

The chip-level serial bus expansion application R&D platform discussed in this paper has achieved good results in practical applications, shortening the time for functional testing of new devices, shortening the development cycle of new products, and increasing the types of serial interfaces as needed. , this platform also provides a good way for beginners to fully understand serial expansion technology.

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