【Introduction】The use of wide-bandgap semiconductors as high-frequency switches provides strong support for achieving higher power conversion efficiencies. As an example, a silicon carbide switch can be implemented as a SiC MOSFET or as a SiC FET in a cascode configuration. This white paper traces the origin and development of SiC FETs to the latest generation and compares their performance to alternative technologies.
Of course, near-perfect Electronic switches have been around for a long time, but we’re not talking about mechanical switches here. Modern power conversion relies on semiconductor switches, which ideally have no resistance when on, infinite resistance and withstand voltage when off, and can switch between switch states at arbitrarily fast speeds with no instantaneous power loss under simple actuation .
In a world where energy and cost are important, these features enable higher power conversion efficiencies for devices such as power supplies, inverters, battery chargers, motor drives, and more. The consequent benefits are reductions in equipment size, weight, and failure rates, as well as lower acquisition and life-cycle costs. Sometimes, just breaking an efficiency threshold can open up a whole new field of application. For example, if electric motor drives are extremely energy-intensive and therefore large and heavy, requiring more battery power, which in turn means increased weight and reduced range on a single charge, electric vehicles will be difficult to achieve. Since the days of Shockley, Budding, and Bratton nearly 75 years ago, engineers have continually strived to improve semiconductor switches closer to ideal switches.
The journey towards the ideal switch
In fact, mechanical switches were used in the first power conversion applications, and mechanical “vibrators” were initially the only option for motor generators for isolated DC conversion or DC power boost devices. However, about a decade after the invention of the transistor, the first “switch-mode” power supplies (SMPS) appeared, and designers have had to deal with available semiconductor technology since then. Although Julius Edgar Lilienfeld proposed and patented the field effect transistor (FET) principle in 1930, FET could not be manufactured at that time. Bipolar transistors, originally using germanium, occupied the early SMPS circuit field.
Initially, bipolar transistors had limited voltage ratings, large leakage in off-state, slow switching and high losses, and complex base drive. Now, power bipolar transistors have low gain and may need to amplify the base current. Stored charge in the base is a big issue, limiting turn-off time and efficiency, so techniques are also employed to precisely tailor the base drive and charge confinement using techniques such as “Becca clamping”, which can bring certain benefits. lower dynamic losses at the expense of conduction losses.
In the 1970s and 1980s, silicon MOSFETs could be used for high power, using vertical conduction paths and planar gate structures, and in the 1990s changed to “trench” structures. However, achievable voltage ratings and on-resistance limit use at higher powers. The late 1970s saw a major advance with the appearance of the Insulated Gate Bipolar Transistor (IGBT), which combined a MOSFET-like gate drive with a bipolar-like conduction path to achieve the advantages of easy gate drive and fixed saturation voltage, Thus the increase in nominal power dissipation in the MOSFET will be proportional to the current rather than the square of the current. However, the IGBT has its own problems, it has a tendency to latch up, which can be disastrous. The “tail current” at shutdown also introduces relatively high dynamic losses and limits the operating frequency. In modern IGBTs, the latch-up problem has now been solved, the tail current has been minimized, and the current and voltage ratings have been greatly increased, so these devices are often used in very high power conversions. However, due to dynamic losses, the switching frequency is still limited to a maximum of tens of kHz.
High switching frequencies are the key to enabling smaller magnetics and power conversion products that are overall smaller and lighter with higher performance control loops, so as MOSFET on-resistance and voltage ratings increase, they are getting more and more Wide range of applications, the frequency has also increased to hundreds of kHz, and the “super junction” type has become a cutting-edge technology. However, the breakdown voltage of silicon is a limiting factor, making it impossible for a given operating voltage and its resulting high on-resistance (RDS) value, the bulk material has to reach a minimum thickness. Paralleling many cells can reduce this value, but will increase the total grain area. This effect can be measured by the “quality factor” of on-resistance per unit area (that is, RDSA), which has spurred a surge of interest in wide-bandgap materials silicon carbide (SiC) and gallium nitride (GaN), which have inherently higher breakdown voltages, higher electron mobility, and higher saturation velocities , High temperature bearing capacity and favorable characteristics, SiC also has good thermal conductivity. Figure 1 shows a comparison of the hallmark features of silicon, SiC, and GaN materials.
[Figure 1. Characteristics of Si, SiC and GaN materials]
Early Development of SiC Devices
SiC devices were developed a decade earlier than GaN and were initially expected to have broader applicability for higher voltage and power ratings. A natural starting point for SiC switches is to consider the development of enhancement-mode normally-off MOSFETs for compatibility with existing Si MOSFET design and fabrication techniques. As with all new technologies, initial difficulties, some predictable and some not, delay the commercialization of devices.
An inherent property of SiC was and is the larger number of lattice defects than silicon, which results in low electron mobility at the gate oxide junction with the SiC channel, which in turn results in relatively high on-resistance. To be cost-effective, SiC wafers must be as large as possible, and it is difficult to maintain low defectivity and wafer flatness at the 6-inch industry standard. SiC MOSFETs also exhibit gate threshold instability with significant hysteresis, making it difficult for gate drive designs to achieve good efficiency and reliability. While the latest SiC MOSFETs have improved and theoretically can use unipolar 0-15V drive, in practice, -5V gate drive voltage is often used for reliable operation. 15V also doesn’t achieve very low on-resistance, so 18V is typically used for best efficiency at the expense of reduced short-circuit withstand capability and a margin drop from a maximum absolute value of typically 19 or 20V. Other issues that have been addressed are gate oxide degradation after short circuit and overvoltage events, and excessive gate oxide electric field stress due to high drain-gate field strengths in the device latched state.
Around 2010, the use of SiC MOSFETs also encountered unexpected difficulties, basal plane dislocations, which are large defects in the lattice, which in fact can grow and move under the action of operating stress. Body diodes conduct electricity from source to drain, so electron-hole carriers are generated, and when the electron-hole carriers recombine, they have enough energy to move and amplify the defect. This is a result of the higher bandgap energy values of SiC and can lead to degradation, i.e. higher leakage current and on-resistance, which in turn lead to higher losses and failures. Today’s SiC MOSFETs have been greatly improved, as have fabrication methods and defect screening, but efforts are still needed to improve die yield and cost-effectiveness, and package performance to achieve low inductance and low thermal resistance.
Alternate method SiC FET
After the birth of wide-bandgap technology, while many semiconductor manufacturers have taken the route of developing SiC MOSFETs using existing production lines, some are starting with a “white paper” and considering other options. The simplest switch implemented with SiC is the JFET structure switch, which has no gate oxide and is a unipolar conducting device, so it does not have some of the limitations of MOSFETs. However, this device has a major drawback, it is a normally-on device, the gate drive voltage is zero, and a negative drive voltage is required to turn off. This is inconvenient by any means and in the worst case leads to the risk of application failure, especially during transients like system on/off. SiC FETs solve this problem, which were first proposed in the 90s and developed around 2010. It combines SiC JFETs with normally-off silicon MOSFETs, preserving the advantages of JFETs over MOSFETs. Figure 2 compares a SiC FET structure (right) with a general SiC MOSFET schematic (left).
[Figure 2. Structure of SiC MOSFET (left) and SiC FET (right)]
SiC FETs use a cascode structure. More sophisticated designers may be familiar with this structure, having seen its original implementation, a combination of tubes designed to reduce noise in audio amplifiers. Over the years, there have been various forms of cascode or “emitter switches” that combine a bipolar transistor or BJT with a MOSFET, with the general properties of a low voltage switch controlling a high voltage switch, and at high voltage ratings with ease There is a good balance between drives. However, circuits employing BJTs are not favored for high voltage applications due to the significant base drive current necessity and slow switching speeds. SiC cascodes, or “SiC FETs,” solve these problems.
As can be seen from the SiC FET schematic shown in Figure 3, when the Si-MOSFET is turned on through the gate, the JFET source and gate are effectively shorted and then the JFET conducts. At this point, current can flow through the JFET and MOSFET drain-source channels, and the conduction losses are corrected by the JFET, since the low-voltage Si-MOSFET on-resistance can be very low compared to the high-voltage SiC JFET. When the Si-MOSFET is turned off, the JFET source voltage rises to a point such that the gate-source voltage exceeds a threshold of minus a few volts, and then the JFET turns off. Due to the device capacitance ratio, the voltage across the Si-MOSFET is kept dynamically low.
[Figure 3. Schematic diagram of SiC FET]
Compared to SiC MOSFETs, SiC FETs have many advantages in electrical performance and practical use. As a switch, on-resistance is an important factor, and SiC JFETs inherently have much better in-channel electron mobility and higher channel density than SiC MOSFETs. The combination of these two means that for a given die area, the on-resistance of a SiC FET is one-quarter to one-half that of a SiC MOSFET, or vice versa, for the same on-resistance per wafer The grains produced can be up to four times the size of the latter. Compared with silicon superjunction MOSFETs, the increase in die count can be up to 13 times. Given that silicon carbide is a material that will likely remain more expensive than silicon, an increase in the number of broken grains per wafer is critical to the success of SiC FET technology. As discussed above, the measure of die viability is the figure of merit, RDSA.
Another figure of merit shown in Table 1 is RDS*EOSS, that is, the trade-off between the on-resistance and the output switching energy of the device, which is caused by the output capacitance. This metric is useful as it shows that on-resistance and conduction losses can be reduced by paralleling more cells in the die, but in addition to increasing area, this directly increases capacitance and thus EOSSincrease, resulting in increased frequency-dependent switching losses. Therefore, RDS*EOSSLow values are favorable.
The gate of the SiC FET is the gate of the Si MOSFET in the cascode structure. It has a threshold of about 5V, is stable, and has essentially no hysteresis, so it can be easily driven at 12V or 15V for full boost and low RDSON, with a large margin from the usual 25V absolute maximum. Nominally, the easy SiC FET gate drive is compatible with silicon MOSFET levels, and even IGBT levels, allowing backward compatibility for existing product design upgrades. In practice, SiC MOSFET cells require a custom drive structure for optimal efficiency and adequate gate overvoltage protection, and GaN HEMT cells undoubtedly do.
Due to the small device size and the insulating effect of Si MOSFETs in the cascode structure, SiC FETs have virtually no gate-to-drain or “Miller” capacitance Crss, thus enabling extremely fast switching. output capacitor COSSand the associated switching energy EOSSare low, as described in Table 1, which also results in fast switching and very small losses. The edge rates are also so fast that in real circuits, SiC FETs must be slowed to limit voltage overshoot and EMI. This can be achieved by adding a gate resistor, but can cause unacceptable control delays at high switching frequencies, so a simple RC snubber circuit is often a better solution. Since the capacitors usually used are COSS About 3 times the capacitor, the dissipation in the series resistance is very small. Figure 4 shows a variant of the common SiC FET device capacitance and its drain voltage in a latched state. Ciss = CGS + CGD(CDSshorted), Crss = CGDCoss = CDS + CGD.
[Figure 4. SiC FET device capacitance]
SiC FET “Body Diode”
In a power converter, a perfect switch should conduct electricity in both directions with low losses. This is also true in circuits such as AC motors and converters with inductive loads, known as “third quadrant” operation. IGBTs cannot meet this requirement and require parallel diodes, while MOSFETs and JFETs made of silicon and SiC can conduct electricity in either direction through the channel under the control of the gate. MOSFETs also have an inherent body diode that JFETs lack, which are “commutated” in hard-switched converters with inductive loads during the “dead time” before the device channel opens through the gate to allow reverse current flow. ” to automatically conduct electricity. This conduction stores a charge, Qrr, which is recovered when the body diode is subsequently reverse biased, and this operation results in a significant power dissipation peak that increases the average value with increasing frequency, thereby reducing efficiency. With silicon MOSFETs, the effect is so severe that they are practically unusable for parts of circuits such as the popular totem-pole PFC stage operating in continuous conduction mode (CCM). Q of SiC MOSFETsrrValues are ten times better than silicon, but SiC FETs are still better because SiC FETs have lower device output capacitance and store very little charge in low-voltage MOSFETs. Comparisons vary by device voltage level, but Figure 5 shows a typical reverse recovery plot for a SiC FET and a similar silicon superjunction MOSFET.
[Figure 5. The reverse recovery charge of a SiC FET cascode is one-hundredth that of a silicon superjunction MOSFET]
While reverse recovery losses for SiC MOSFETs and GaN devices are low enough or none at all, the voltage drop in reverse conduction is another story. This can cause significant losses in the power converter during dead time. Silicon superjunction MOSFETs introduce a diode drop typically around 1V, while SiC MOSFETs are much worse, with body diode drops easily reaching 4V. In the third quadrant operation, the voltage drop V of the GaN HEMT cellsdis the sum of the I*R channel voltage and the gate threshold voltage minus the gate-source voltage, which is Vsd = (Vth-Vgs)+(Isd*Ron).
The gate threshold of GaN is typically 1.5V, so at high currents the overall voltage drop can be high. If the gate drive voltage is negative to achieve turn-off, which is common, this voltage Vgswill add to the source-drain voltage drop, resulting in several volts of Vsd, which is much worse than other techniques. The channel resistance of a SiC FET produces an I*R drop during conduction from source to drain, similar to a GaN device, but the drop increases only across the body diode of a cascode low-voltage Si MOSFET voltage, this value is relatively low. The final forward voltage is typically around 1.5V, which is stronger than SiC MOSFETs or GaN.
Proving the reliability of SiC FETs
A wide bandgap switch is robust, especially because of its inherent high withstand and high breakdown voltage capability, a particular advantage of SiC FETs is the absence of the SiC gate oxide that is present in SiC MOSFETs, which is degraded by high electric fields question. A Si-MOSFET in a cascode structure is a robust low-voltage device with high threshold voltage and thick gate oxide, protected by a built-in voltage regulator clamp. In real-world applications, SiC FETs have performed very reliably, and their devices are now often able to achieve automotive AEC-Q ratings. Another important consideration is stability during unexpected stress events, such as overvoltage and short circuit events. SiC FETs have very strong avalanche capability, which is achieved by JFET drain-gate breakdown. The resulting current through Rg in Figure 3 will cause the voltage to drop, turning on the JFET and limiting the overvoltage. Si MOSFETs now avalanche, but their avalanche is highly controllable because avalanche protection diodes are included in the manufacture of each cell, and avalanche dissipates very little power. SiC MOSFETs also have avalanche ratings, but GaN HEMT cells do not, which has led manufacturers to voltage ratings of devices lower to allow ample margin between operating voltage and damaging breakdown voltage.
SiC FETs also have good short-circuit current characteristics. At high currents, the gradient of the voltage drop across the channel causes a natural “pinch-off” effect to limit the current. Short-circuit current is not affected by gate voltage, unlike MOSFETs and IGBTs, and the positive temperature coefficient of on-resistance of the SiC FET channel also helps reduce current limiting and stress propagation across individual cells of the die. The effect is so consistent that SiC FETs can be used as precise current limiting devices in linear circuits. A typical test in automotive applications is to subject the device to short-circuit current for at least 5µs, and Figure 6 shows that a 750V SiC FET can withstand stress for 8µs without degradation. Figure 7 shows the effect of increasing on-resistance with temperature when using a 1200V rated SiC FET, reducing the short-circuit current to its final value, which is largely independent of the initial junction temperature.
[Figure 6. SiC FET withstands 8µs short-circuit stress from 400V bus]
[Figure 7. SiC FET short-circuit current is not affected by initial junction temperature]
In order to maintain reliability, the temperature rise and gradient of SiC FETs in the package should be minimized, and here, the thermal conductivity of SiC is more than 3 times that of silicon or GaN is an advantage. The latest devices also use silver sintering technology for die attach instead of soldering, which increases the thermal conductivity of the junction by a factor of 6, maintaining low junction and high reliability.
Other SiC FET applications
SiC FETs are naturally suitable for high-efficiency power converters, rated up to 1700V, for typical industrial three-phase applications. However, the cascode principle can be easily generalized by “stacking” SiC JFETs on top of the control Si MOSFET (Figure 8). Modules rated at 40kV have been developed using this principle.
[Figure 8. The stacked cascode principle can be used in high voltages rated up to tens of kilovolts]
As mentioned above, SiC JFETs have a characteristic that the saturation current is almost invariant with gate-source and drain voltages, which is an advantage in circuit protection applications such as current limiters or circuit breakers. Figure 9 shows a self-biased circuit breaker concept using a SiC FET cascode structure, a true “two-terminal” structure without external auxiliary power rails and internal DC converters.
[Figure 9. Concept of two-terminal self-biased circuit breaker]
Improvements in performance and value
SiC FETs have progressed with each generation of technology, the “fourth generation” being the latest generation with many advancements, including the range of voltages available, cell density for better on-resistance, and improved thermal performance. Sintered die bonding method. “Substrate thinning” techniques have been employed because the channel resistance is so low that conduction losses through the substrate itself also become a limiting factor. Device improvements are also ongoing, especially reducing the output capacitance COSS. This reduces losses in hard-switching topologies, such as totem-pole PFCs in continuous conduction mode, and also enables soft-switching resonant circuits to increase operating frequencies, such as LLC or PSFB circuits. Switching edge rates are now so fast that devices are classified as “ultrafast” and intentionally slowed down “fast” for applications where the edge rate is not critical to performance but can cause EMI and shoot-through problems, such as motor drive.
Packaging has also advanced compared to the first generation of SiC FETs, which placed Si MOSFET and SiC FET dies side-by-side and connected by wire bonds. This advancement brings flexibility, such as in TO-247 packages, but to achieve lower cost and higher performance, a “stacked” die arrangement is now common, allowing larger dies to achieve high currents , especially when paralleling devices in small modules. The soldered die attach method has been replaced by silver sintering for better thermal performance. TO-220, TO-247, and D2PAK packages remain popular as they support retrofitting SiC FETs for older designs, even those using IGBTs. Four-pin versions of these packages feature a “Kelvin” source connection, which alleviates problems caused by source pin inductance interfering with the gate drive loop.
In addition to this, the adoption value of SiC FETs is increasing due to their electrical properties, and SiC FETs also have cost reduction options due to increasing yields and the move to 8-inch wafers.
SiC FETs are a compelling solution
With the latest generation of SiC FETs, we are now one step closer to ideal switching. Conduction and dynamic losses have become unprecedentedly low, enabling high-frequency power conversion stages to reach 99%+ energy efficiency with corresponding energy savings, size reduction and weight reduction. Designers define “ideal” to mean more. They also want devices that can be driven easily, come in a convenient package, have stable characteristics, and operate under a variety of operating conditions and fault conditions. At the same time, device end-users expect the end product to be reliable and cost over the entire life cycle a substantial improvement over earlier technology implementations. UnitedSiC offers SiC FETs that fulfill their aspirations, with devices ranging from 650V to 1700V in voltage ratings and on-resistance down to 7 milliohms. UnitedSiC also provides the FET JET calculator as a design aid to quickly select devices for a range of power conversion topologies and predict the performance of any device in these topologies, including PFC-level topologies and isolated/non-isolated DC converter topologies.
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