How to speed up design and debugging? A breakthrough, scalable, intuitive and easy-to-use power-up sequencing system is the key!

【Introduction】It is no secret that Electronic systems in all walks of life are becoming more and more complex. As to how this complexity permeates the power supply design, it is not so obvious. For example, functional complexity is typically addressed through the use of ASICs, FPGAs and microprocessors, incorporating richer application features in smaller form factors.

It’s no secret that electronic systems in all walks of life are becoming more complex. As to how this complexity permeates the power supply design, it is not so obvious. For example, functional complexity is typically addressed through the use of ASICs, FPGAs and microprocessors, incorporating richer application features in smaller form factors. These devices provide different digital loads to the power system, requiring the use of multiple voltage rails at different power levels, each with highly individual voltage rail tolerances. Likewise, proper power-on and power-off sequencing is important. Over time, the number of voltage rails on a circuit board has multiplied, making timing and debugging of power systems more complex.


The number of voltage rails required for an application board is closely related to the complexity of the board. Power supply designers are faced with boards that may require as few as 10 voltage rails, or as many as 200 voltage rails. A sequencer device requires a maximum of about 16 voltage rails, and this number is easy to achieve when designing. Once the number of voltage rails exceeds the number supported by a single sequencer, complexity rises dramatically, requiring designers to understand the various variations of each sequencer and how they fit into complex systems.

Often, cascading multiple sequencers in high voltage rail count systems is not easy to implement. In a cascaded system, the complexity grows exponentially as the number of voltage rails increases linearly. Designers can implement sequencer cascades in innovative ways to simplify designs, such as using a ping-pong mechanism or sharing fault and power good states through dedicated digital signals. While these solutions are adequate for relatively simple timing, they are clearly inadequate for complex power-up/power-down sequences.


●Complete monitoring and sequencing solution for up to 17 power supplies

Expandable to 257 supplies with additional ADM1266 IC connected to 2-wire inter-device bus

● Fully programmable sorting engine

17 power failure detectors for real-time monitoring of power

0.4 V to 15 V on VH1 to VH4 (VHx)

0.4 V to 5 V on VP1 to VP13 (VPx)

The device is powered by the higher of the VH1 and VH2 inputs for improved operational reliability redundancy

●12-bit ADC for readback of all monitored voltages

●Black box non-volatile fault record

16 Programmable Driver Input/Output (PDIO)


9 voltage output 8-bit DACs allow voltage headroom adjustment via DC/DC converter trim/feedback nodes

●Main memory and backup memory

●Compatible with industry standard PMBus interface

●In a 9 mm × 9 mm 64-pin package

The ADM1266 is truly scalable to address complexity. It is the latest in the ADI Super Sequencer® family of super sequencers. When connecting multiple ADM1266 devices, a dedicated two-wire inter-device bus (IDB) is required for communication. Each ADM1266 can monitor and control the timing of 17 voltage rails, and as long as all these devices are connected to the same IDB, up to 16 ADM1266 devices can be connected in parallel to monitor and control the timing of 257 voltage rails.

The ADM1266 uses one master device and the other ADM1266 devices act as slave devices. These devices use a parallel architecture where each individual ADM1266 connected to the IDB transitions to the same next state based on system conditions, ensuring that each ADM1266 on the bus is synchronized. The bus communication is transparent, so the designer feels the same as creating timing for a single ADM1266 device as for 16 ADM1266 devices. A clear advantage of this system is that designers only need to learn how to use one device for simple and complex designs, rather than having to learn multiple times for each different device. Cascading multiple devices is as simple as connecting them to the same IDB, as shown in Figure 1.

How to speed up design and debugging? A breakthrough, scalable, intuitive and easy-to-use power-up sequencing system is the key!

Figure 1. Multiple ADM1266s can be grouped together via an IDB to easily extend timing.

Event-Based Sequencing Scheme

Modern sequencers must not only monitor voltage rails, they must also react to digital signals. Traditional time-based timing controllers have fixed signals, get custom effects, and have limited functionality.

Let’s take a motherboard with optional daughterboards as an example. The sequence controller monitors the signal detection of the daughter card: when the signal exists, the sequence controller will call out the voltage rail on the daughter card; when the signal does not exist, the sequence controller continues to execute the sequence control program of the main board, and when the power supply reaches a good state time ends. Most legacy timing controllers do not provide this daughter card signal detection. Furthermore, this requirement varies with the application and can be addressed using general purpose input output pins (GPIO).

Another example involves powering ASICs and FPGAs, where the system requires the ASIC to be fully powered up and running before powering the FPGA. In this case, the sequencer sequentially pulls out the ASIC power and then waits for a digital power good signal from the ASIC. Once the ASIC power good signal is acknowledged, it will wait 100ms before continuing to power the FPGA. An event-based timing controller is required to generate this complex timing. In systems with multiple sequencers, it is important to share event information on one device with other devices on the board so that they act in unison.

Voltage monitors, OV and UV comparators, digital signals such as GPIO and PDIO, timers, variables, and messages from the IDB, all feed the feature-rich ADM1266 timing engine to trigger events. Users can easily create complex state machines that monitor various events and take appropriate action.

Speed ​​up system design

Traditionally, the user experience of designing a power-up sequenced system using a single sequencer has been very different from the experience of designing a system that requires the use of multiple sequencers. That said, designs that control 16 voltages with a single timing controller are often straightforward: Designers can use a software graphical user interface (GUI) to configure each voltage rail and its timing. The process is usually repeated manual select/set operations for 16 voltage rails. Now imagine a design with 5 sequencers and 80 voltage rails. Manually configuring 80 voltage rails using the GUI is time-consuming and error-prone. Designers must also determine how to best cascade multiple devices and allocate the resources of the five sequencers to the 80 voltage rails. Most software-aided design tools don’t actually help at all. The user must understand the specific functions of the sequencer IC and issue clear instructions through the GUI, and each project requires a lot to learn quickly.

The ADM1266 takes a different approach. It uses PC-based ADI ™ for configuration and debugging, not just configuring the various settings of the ADM1266. ADI Power Studio is a complete development and debug tool that helps designers achieve robust timing. It allows designers to handle power systems at a higher level than traditional GUIs. For example, built-in wizards help designers set up and configure 80 voltage rails in minutes, a task that would take hours if done manually. Figures 2 and 3 show some interface examples.

Figure 2. ADI Power Studio can customize voltage rail names, which can be substantial.

Figure 3. Configure the entire system in one step. Regardless of the number of voltage rails, the system voltage rail wizard guides the designer through the same interface through the sequence configuration process. Note that the user-defined voltage rail names help to quickly and easily identify each voltage rail.

Designers must first create a virtual state machine to meet the requirements of the system. In a single sequencer design (≤17 voltage rails), the GUI’s virtual state machine matches the sequencer’s state machine. As more sequencers are added, the difference between a virtual state machine and a single sequencer state machine arises, requiring additional steps in the state machine when devices communicate with each other about various events.

For example, a designer monitors two voltage rails on sequencer 1 and two voltage rails on sequencer 2. The design requires that if any of the four voltage rails fail, then everything shuts down. Actually, since there are two devices here, the fault signal must be shared between them. The virtual state machine of the system and the state machine of each device are shown in Figure 4.

Figure 4. Virtual state machine versus device-level state machine.

As the number of voltage rails increases, the sequencing requirements become more complex, and the difference between system-level virtual state machines and device-level state machines becomes larger. Designers know their design goals, but they must achieve it through sequential controllers working together, a process that is time-consuming and often buggy. ADI Power Studio automates much of the state machine creation process. The user uses the GUI to design the virtual state machine, while ADI Power Studio handles the complex communication between the various timing controllers through the compiler. This enables designers to create complex state machines through a flexible, intuitive process.

Powerful debugging tools

In the process of developing any complex system, there are bound to be vulnerabilities. Ideally, most bugs would be rooted out during development as they appeared, but some bugs would make their way into production unnoticed. In either case, it is critical that system designers have the right tools to quickly identify failures and make changes to fix them, often the time designers spend debugging far beyond pure design time. Typical faults include faulty voltage rails and wrong logic levels of signals.

Now, continuing with the example of a board with 80 voltage rails, it is not uncommon during board design for one of the voltage rails to fail. Failures can be the result of component-level or configuration-level design flaws. In any case, finding the cause of the problem starts with finding the voltage rail that caused the fault. The problem is that in typical timing, if any one of the voltage rails fails, the sequencer shuts down all the voltage rails. This shutdown behavior, while reliable for production-grade products, hinders debugging during the design phase because such individual faults can be hidden within the faults of the overall system. Confused designers. Designers are unlikely to monitor all 80 voltage rails at the same time, so it is almost impossible to find out when a voltage rail fails in the first place.

In an ideal debug system, once a fault-prone voltage rail is identified, the other rails remain powered so that the rest of the system can remain operational while the behavior of the faulty rail is checked. While forcing a timing configuration change can accomplish this, debugging timing in a way that breaks it is a cumbersome approach at best.

ADI Power Studio and the ADM1266 feature advanced debugging tools commonly found in software design environments to simplify the debugging process. The first debugging tools came in the form of breakpoints, in which timing stopped advancing at certain states. In systems with multiple ADM1266 devices, all ADM1266 devices will transition through a state machine, stopping when a state containing a user-defined breakpoint is reached. This timing pause allows the designer to debug a faulty voltage rail, or to confirm the cause of the wrong logic level of a signal.

Designers can also apply breakpoints to all states for step-by-step inspection of the entire timing. The single-step application method is used to check the pre-bias start-up condition of the voltage rails before enabling them. Designers can single-step through the power-up sequence to see if voltage is present at the output of any voltage rail that may be disabled—this is displayed in the monitor window section of ADI power Studio. Figure 5 shows an example of a user-defined breakpoint.

Figure 5. Breakpoints allow designers to pause timing in any state to deepen debugging.

Another debug tool is the black box logging feature, where the ADM1266 captures a snapshot of the state of all voltage monitoring and digital pins when the black box is triggered by a critical event. Once the black box is triggered, it records information such as the state at the time of the event, the previous good state, the time the event occurred, the number of times the component was powered up, and the number of times it failed. This helps designers pinpoint faults and quickly diagnose the cause.

In production applications, the black-box feature plays a key role in capturing fault conditions and assisting with maintenance and upgrades. It can also be used as a debugging tool during development. For example, when a design is subject to hot chamber testing or mechanical testing, probing with benchtop lab equipment is not possible, but a black box can record failures for later review. Figure 6 shows a screenshot of the black box recording.

Figure 6. Black-box status monitoring takes a snapshot of the status of user-defined events. Black box triggers can be applied to production systems to help troubleshoot in the field, as well as for maintenance and commissioning.

in conclusion

To address increasingly complex power-up sequencing requirements, solutions must be scalable, feature-rich, and intuitive to use. ADI Power Studio and the ADM1266 17-channel sequencer meet these conditions, using advanced design and debug tools to reduce development and debug time. This frees designers to spend more time innovating and building robust solutions.

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