“The server, storage, and networking markets now routinely use PCI Express® (PCIe®) to interconnect various devices, and applications in backbone and I/O products for industrial automation, Internet of Things, consumer devices, and automotive electronics are also taking it seriously. Pros, expanded adoption of PCIe. In order to meet user expectations and ecological design requirements in related fields, the PCI Special Task Force (PCI-SIG) has successively introduced various power-saving innovation projects in the specifications that continue for multiple generations, as well as improved reliability, availability, maintainability (RAS). ) various functions.
Superior power management and error handling enhances PCIe’s reliable performance as a competent storage, networking, backbone and I/O interconnect technology in a variety of applications
By: Jen Lee, Marketing Associate, Diodes Corporation
Wide range of connectivity features
The server, storage, and networking markets now routinely use PCI Express® (PCIe®) to interconnect various devices, and applications in backbone and I/O products for industrial automation, Internet of Things, consumer devices, and automotive electronics are also taking it seriously. Pros, expanded adoption of PCIe. In order to meet user expectations and ecological design requirements in related fields, the PCI Special Task Force (PCI-SIG) has successively introduced various power-saving innovation projects in the specifications that continue for multiple generations, as well as improved reliability, availability, maintainability (RAS). ) various functions.
Today’s PCIe 3.0 switches support data transfer speeds of up to 8GT/s per lane, combined with high bandwidth and the latest power management and RAS features to meet the needs of mobile and embedded product applications.
Reduce power consumption
As more portable, mobile, and IoT product applications seek to leverage PCIe attributes, interconnect power consumption during device use and in standby is naturally an increasingly critical focus. The scalability of PCIe allows designers to customize the interface bandwidth and power consumption of the in-use mode according to product application projects. Diodes Incorporated offers a family of PCIe 3.0 switches including PI7C9X3G606GP, PI7C9X3G808GP and PI7C9X3G816GP, which provide 6, 8 and 16 lanes of PCIe 3.0 connectivity, respectively.
Starting from the PCIe 3.0 generation, the link training state machine (LTSSM) defines various link states, which ensures that the device consumes power when it is in use, and consumes power when it is not in use. Significant savings, system performance is not affected.
L0 is the power state when the link is operating normally. If no data is being transmitted, the link enters the L1 state, which turns off part of the PCIe transceiver logic. In addition, in the case of only transmitting data in one direction, there is also a state of L0s, which is dedicated to two devices on the link to independently turn off the transmitter to meet more detailed needs.
Considering that there are analog circuits in the physical layer, each channel will consume a few milliwatts when idle, and another L1 substate is defined to turn off the analog components to ensure maximum power savings. In the L1.1 substate, the transceiver PLL is turned off, while the L1.2 substate turns off the common-mode voltage keeper, further reducing power. To achieve the low power states of L1.1 and L1.2, the recovery delay will be slightly longer. Table 1 illustrates the characteristics and performance of the L1 and L1.1/L1.2 substates.
Table 1. Comparison of power saving performance and performance of L1 and L1 substates. (Data source: https://www.synopsys.com/designware-ip/technical-bulletin/reduce-power-consumption.html)
To achieve this, and to ensure that the link enters the most appropriate low-power state to resume operation when needed, the Latency Tolerance Report (LTR) allows the host to determine the maximum time to wait before interrupting service from any particular device . As for the buffer empty/fill optimization (OBFF) function, it allows the host to send system status information to the device, which can shut down the host processor and memory subsystem, maintain a low power state for a longer time, and achieve maximum savings. electrical performance.
There are also other low-power states available, such as L2 with the transceiver completely turned off and L3 with the transceiver turned off and power removed, which helps ensure the power consumption of the PCIe interconnect during device idle periods to a minimum. This is especially important for IoT product applications and devices such as laptops and tablets, effectively avoiding accidental battery drain when the device is idle.
Diodes’ PCIe switches PI7C9X3G606GP, PI7C9X3G808GP, and PI7C9X3G816GP support the aforementioned low-power link states and sub-states, and can also close any empty hotplug ports until they are needed to be opened again. With power management schemes for startup and continuous operation, they consume extremely low power in all modes. At full load and 80°C junction temperature, the PI7C9X3G808GP consumes only 2.9W. The industrial temperature range of the associated unit is: -40°C to 85°C.
The new switch products also feature built-in PCIe 3.0 clock buffers to help designers optimally tune the functionality and performance of their product applications. The buffers support a variety of PCIe 3.0 reference frequency architectures, including generic, independent reference spread spectrum (SRNS) and independent reference spread spectrum (SRIS).
Addressing RAS in PCIe
Among certain IoT devices and robots, product applications that are mission-critical or have a high priority on safety require a high degree of reliability, availability, and serviceability. At this point, appropriate mechanisms must be in place to ensure that the interface can function properly under changing internal or external conditions, and can recover and resume normal operation after a data miss.
The basic requirements for ensuring end-to-end data integrity are covered in the various basic and optional functions specified by the PCIe specification. These include a 32-bit link-by-link cyclic redundancy code (LCRC) for error detection, and an acknowledgment mechanism (ACK/NACK) to allow replay of requests. Acknowledgment timeout verifies that the link partner is functioning properly, allowing the link to be retrained without reception. There is also a transaction layer 32-bit CRC (ECRC) for detecting end-to-end data integrity. Additionally, a fail-safe mechanism for potential timeouts can be provided to ensure that the link partner returns to a known state and the LTSSM is re-initialized.
If desired, Advanced Error Reporting (AER), a PCIe feature, can be used to expand error signaling and logging. The error register displays the status of each error in the PCIe device function, indicates the severity and source of the error, and evaluates correctable and uncorrectable errors to ensure that the system detects faults smoothly and enters a safe state.
Diodes’ PI7C9X3G606GP, PI7C9X3G808GP and PI7C9X3G816GP not only support various data integrity functions, but also support the provisions of the PCIe specification to handle sudden hot unplugging of connected devices. When the device is removed, the normal response to the request timeout is slow, which may cause data errors and task interruption; when the device is removed, as long as it can respond quickly, it is enough to avoid various errors caused by accidental hot removal.
The switch also supports PCIe-selective Downstream Port Containment (DPC), which specifically handles errors that cannot be corrected. A DPC-capable port automatically disables a link when an uncorrectable error is detected, preventing the spread of corrupted data while allowing for smooth device removal. When the device is removed, the status flag is cleared and the link can be retrained for the newly connected device. These switches support hot-plugging for both upstream/downstream ports and serial/parallel hot-plugging types.
Additional features include support for Cross-Domain Endpoint (CDEP) mode, where a port is configured as CDEP, connecting to another host instead of an endpoint. This design provides failover redundancy, or ensures smooth communication between two processors, or even between one processor and another smart switch configured in processor mode. Individual devices have four physical direct memory access (DMA) channels, increasing the efficiency of data exchange between host and endpoint; these physical channels can be shared, allowing eight pairs of locations to transfer data simultaneously.
The popularity of PCIe is expanding beyond data centers, servers, and personal computers to a wider range of fields, including industrial, IoT, and consumer device markets. Adding more powerful features to the latest specification minimizes power consumption while increasing RAS. PCIe switches that support related functions allow system designers to take full advantage of the speed advantages and multi-function features of this interconnect technology in power-conscious and critical product applications.
The Links: VUO55-12NO7 G190EG01 V1