Continued increases in clock frequencies make phase noise and jitter increasingly important in system timing. This article introduces its concept and its impact on system performance, and provides effective methods to reduce phase noise and jitter at the board level, chip level, and unit module level, respectively.

As clock speeds in communications systems move into the GHz range, phase noise and jitter, two critical factors in analog design, are beginning to play an increasingly important role in the performance of digital chips and boards. In high-speed systems, timing errors in clock or oscillator waveforms can limit the maximum rate of a digital I/O interface. Not only that, but it can also increase the bit error rate of the communication link and even limit the dynamics of the A/D converter. Scope.

With this trend, designers of high-speed digital equipment have also begun to pay more attention to timing factors. This article introduces digital designers to the basic concepts of phase noise and jitter, analyzes their impact on system performance, and presents common circuit techniques for minimizing phase jitter and noise.

**What is phase noise and jitter?**

Phase noise and jitter are two different ways of quantifying the same phenomenon. Ideally, a perfect pulse signal with a fixed frequency (take 1 MHz as an example) should have a duration of exactly 1 microsecond, with a transition edge every 500ns.

But unfortunately, such a signal does not exist. As shown in Figure 1, the length of the signal period will always vary, resulting in an uncertain arrival time of the next edge. This uncertainty is phase noise, or jitter.

**Jitter is a time domain concept**

Jitter is a measurement of the time-domain variation of a signal, which essentially describes how far the signal period deviates from its ideal value. Typically, periodic variation of signals below 10 MHz is not classified as jitter, but as offset or drift. There are two main types of jitter: deterministic and random. Deterministic jitter is caused by identifiable interfering signals that are usually limited in magnitude, have a specific (rather than random) cause, and cannot be statistically analyzed. There are four main sources of deterministic jitter:

1.

2. EMI radiation on sensitive signal paths: Power supplies, AC power lines, and RF signal sources are all EMI sources. Similar to crosstalk, when there is EMI radiation nearby, the noise current induced on the timing signal path modulates the voltage value of the timing signal.

3. Power plane noise in multilayer substrates: This noise may change the threshold voltage of the logic gate, or change the ground reference level of the threshold voltage, thereby changing the voltage value required to switch the gate circuit.

4. Multiple gates transitioning to the same logic state at the same time: This condition can cause current spikes to be induced in the power and ground planes, which can change the threshold voltage.

Random jitter refers to timing variations caused by less predictable factors. For example, temperature factors, which can affect the mobility of semiconductor crystal materials, can cause random changes in carrier current. Additionally, variations in semiconductor processing, such as uneven doping density, can also cause jitter.

One of the most basic properties of random jitter is randomness, so we can use the Gaussian statistical distribution to describe its properties. For example, 100 consecutive measurements of the oscillation period of a clock oscillator containing only random jitter factors will result in a Gaussian (or normal) distribution. Contains 68.26% of all periodic measurements within plus or minus 1 standard deviation of their mean and 95.4 % of all measurements within +/- 2 standard deviations of their mean, +/- 3 standard deviations 99.73% of measurements are within range and 99.99366% are within +/- 4 standard deviations.

From this normal distribution, we can derive two common definitions of jitter:

1. Peak-to-peak jitter, which is the difference between the smallest measured value and the largest measured value on the normal curve. In most circuits, this value increases with the number of measurement samples and can theoretically reach infinity. Therefore, this measurement is not meaningful.

2. RMS (root mean square) jitter, which is the value of the first standard deviation of a normal distribution. This value does not change much as the number of samples increases, so this measurement is more meaningful. But this measurement is only valid in a pure Gaussian distribution, and if there is any deterministic jitter in the distribution, it is wrong to use the first-order variance over the entire jitter histogram to estimate the likelihood of jitter present.

3. Multiple random jitter sources can be added in RMS fashion. But to get the total jitter, the peak-to-peak value is used to add random and deterministic jitter.

**Phase noise is a concept in the frequency domain**

Phase noise is another measure of timing changes in a signal, the results of which are displayed in the frequency domain. Figure 2 uses an oscillator signal to explain phase noise.

If there is no phase noise, then the entire power of the oscillator should be concentrated at frequency f=fo. But the presence of phase noise spreads some of the oscillator’s power into adjacent frequencies, creating sidebands. As can be seen from Figure 2, at an offset frequency a reasonable distance from the center frequency, the sideband power rolls off to 1/fm, where fm is the difference between that frequency and the center frequency.

Phase noise is generally defined as the dBc/Hz value at a given offset frequency, where dBc is the ratio of power to total power at that frequency in dB. The phase noise of an oscillator at an offset frequency is defined as the ratio of the signal power to the total signal power within a 1Hz bandwidth at that frequency.

In Figure 2, the phase noise is expressed as the ratio of the area of the rectangle within the 1Hz bandwidth at the offset frequency fm to the area contained under the entire power spectrum curve, which is approximately equal to the difference between the height of the curve at the center frequency and the height of the curve at fm Difference. This curve shows the power spectrum of an oscillator with noisy phase angles, which themselves fluctuate in Figure 3.

Figure 2 shows the power spectrum of the oscillator, while Figure 3 shows the spectrum of the noise phase angle, also known as the spectral density of the phase fluctuation. For an offset frequency far enough from the center frequency, the phase noise measured in dBc/Hz from the power spectrum shown in Figure 2 is equal to the value of the phase fluctuation spectral density at that frequency shown in Figure 3.

The density spectrum in Figure 3 is represented on a logarithmic scale, where the phase noise sidebands drop at a rate of 1/fm2 or 20 dB/decade. In fact, somewhere in the noise sideband, the phase noise may drop by 1/f3, 1/f2, or even 1/f0, depending on the associated noise process.

The region where the rate of decline is 1/f2 is called the “white frequency” variation region, and the phase variation in this region is caused by white or uncorrelated fluctuations in the oscillator period. The behavior of the oscillator in this region is determined by the thermal noise of the components in the oscillator circuit. When the offset frequency is low enough, the flicker noise of the element usually also plays a role, causing the spectral density in this region to drop at a rate of 1/f3.

In addition, it is worth noting that when the offset frequency in Figure 3 tends to 0, the sideband noise tends to infinity. This is exactly the timing jitter behavior expected in a free-running oscillator.

**How to Convert Phase Noise to Jitter**

As mentioned earlier, jitter and phase noise characterize the same phenomenon, so it would be interesting to derive the value of jitter from a measurement of phase noise. The derivation is described below: Each oscillator has its phase noise plot, an example is given in Figure 4. The graph plots the phase noise of an oscillator in the frequency band from 12 kHz to 10 MHz. In the figure, L(f) gives the distribution of sideband noise as a power spectral density function in dBc. The power at the center frequency is not important because the jitter only reflects the relative power value at the “pure” center frequency with respect to the phase noise (ie modulation). The total noise power in the sidebands can be obtained by integrating the L(f) function over the entire frequency band of interest (in this case, the 12 KHz to 10 MHz band).

What is calculated is the power in the frequency band of the phase modulation noise, which is the cause of the jitter. From this, we can also derive the value of RMS jitter by the definite integral as follows.

The RMS jitter due to this noise power can be found as:

Jitter values can also be expressed in other units, such as unit time (UI) or time. Divide the above equation by the center frequency in radians to convert jitter to time, as shown in the following equation:

Using the noise power values plotted in Figure 4, we can calculate the RMS jitter for a 312.5MHz oscillator. Integrating the phase noise curve from 12 kHz to 20 MHz gives -63 dBc:

Therefore, the RMS phase jitter value in radians can be obtained as follows:

You can also convert this jitter value unit to picoseconds:

The typical total jitter value for the same 312.5 MHz oscillator is around 5ps RMS.

In the end, our calculated jitter value of 0.72 ps RMS is only a small percentage of the maximum jitter.

**How to Minimize Phase Noise and Jitter on Your Circuit Board**

Board designers can reduce deterministic signal jitter on the board through two key techniques:

1. Transceive and receive signals fully differentially: Conventions such as LVDS or PECL that transmit and receive signals differentially greatly reduce the effects of deterministic jitter, and this differential path also eliminates all interference and crosstalk on the signal path. Since this kind of signal transceiver system has a high ability to suppress common mode noise, the differential form has a tendency to eliminate jitter.

2. Route carefully: Whenever possible, avoid spurious signals that may affect the signal path through crosstalk or interference. Traces should be as short as possible and should not cross traces carrying high-speed switching digital signals. If a differential signal transceiver system is used, the two differential signal lines should be placed as close together as possible to take advantage of their inherent common-mode noise rejection characteristics.

**How to Minimize Phase Noise and Jitter in Chips**

At the chip level, jitter can be minimized using the following design techniques:

1. Differential Signal Transceiver: Even if a single-ended signal enters the chip, it is best to convert it to a differential signal in the chip, for the same reasons described in the previous section.

2. Route signal paths carefully: Care must be taken when routing timing-sensitive signal paths, keeping the traces as short as possible, and avoiding crossing any digital signal lines. As long as conditions permit, it is best to Display these signal paths on the screen. For example, a signal path on the second metal plane can be sandwiched between the first and third metal planes, and both the first and third metal planes are connected to a clean ground.

3. Proper selection of buffer size: If buffers are used to distribute signals among modules, care must be taken in the choice of drive strength. Insufficient drive will cause the rising/falling edge of the signal to be too slow, giving an opportunity for noise.

4. Keep the floor and ground clean: The noise floor and ground are the main causes of deterministic jitter. In a chip with multiple simultaneous digital outputs, ground bounce noise can reach hundreds of millivolts, or even 1 volt. To reduce ground bounce noise, there should be as many power supply pairs as possible on the chip, and these power supply pairs should be as close as possible to the digital outputs.

5. Use a separate clean ground plane: In circuit design, it is best to separate the power supply for digital circuits from the power supply for sensitive analog circuits such as oscillators or PLLs. Digital circuits, especially power supplies with high drive output digital circuits, are likely to introduce noise, and once such power supplies are used in sequential circuits, they can also be a major cause of increased jitter. Therefore, power supply filtering can even be used for circuits such as PLLs to further reduce the effects of power supply noise.

**How to Minimize Phase Noise and Jitter in Element Modules**

When designing unit modules, the following techniques can be used to reduce jitter: 1. Utilizing tail currents – There is a direct relationship between the currents used in sequential circuits and phase noise. For example, increasing the tail current of a differential pair must result in improved jitter performance. So we must find a balance between reducing jitter and reducing power consumption, selectively increasing the current of the most sensitive circuits where appropriate. 2. Careful layout – Care must be taken when laying out cells that can cause phase noise, matching components (such as inputs connected to a differential pair) should be oriented in the same direction and as symmetrical as possible. This method helps to improve the matching degree between components by making the components to be matched have the same process gradients. The resistors should be as wide as possible to reduce the Delta W effect. If possible, use the same kind of resistors, even the same size and value, throughout the circuit to help track all process and temperature variations.

In conclusion, to minimize jitter, care must be taken at all design layers. High-speed digital designers should consider the effects of phase noise and jitter at every step of the design process.

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