Domestic 7nm has a letter, SMIC can do it without EUV lithography machine

SMIC, the largest wafer foundry in China, has mass-produced the 14nm process in the Q4 quarter, contributing 1% of revenue, and this process can meet 95% of domestic chip production.

The most important issue of SMIC’s 14nm process is production capacity, which is mainly produced in the SMIC South 12-inch wafer fab in Shanghai. At the end of last year, about 1,000 wafers were produced, and the output was very low.

According to Liang Mengsong, co-CEO of SMIC, 14nm monthly production capacity will reach 4K in March this year, 9K in July, and 15K in December.

SMIC’s 14nm production capacity should not continue to increase after 15K wafers/month, and there are newer processes.

Among them, the improved 12nm process based on 14nm has also entered the stage of customer introduction. Compared with the 14nm transistor size, this process has further reduced the power consumption by 20%, improved the performance by 10%, and reduced the error rate by 20%.

However, the 14nm process still has a gap of 2-3 generations compared with the processes of TSMC and Samsung, and it cannot meet the current highest performance level of processors, so SMIC is still developing a newer generation of N+1 and N+2 processes.

At this financial report meeting, Dr. Liang Mengsong also disclosed the situation of N+1 and N+2 generation processes for the first time. He said that compared with 14nm, the performance of N+1 process has been improved by 20%, the power consumption has been reduced by 57%, and the logic area has been reduced by 63%. , the SoC area is reduced by 55%.

SMIC has not made it clear whether the 10nm process will be skipped after 14nm, so it is uncertain whether this N+1 is 10nm or 7nm, but according to the above statement, N+1 can basically be determined to be a 7nm-level process, because the reduction of the chip area by 55% means that With the transistor density doubled, which exceeds the evolution level of the 14nm to 10nm process, TSMC has doubled the density from 14nm to 7nm.

However, Liang Mengsong also mentioned that the N+1 generation process is very similar to the 7nm process in terms of power consumption and stability, but the performance is not as good. The industry standard is to increase by 35%, so SMIC’s N+1 process is mainly for low power consumption.

After N+1, there will be N+2. The power consumption of these two processes is similar. The difference lies in performance and cost. N+2 is obviously for high performance, and the cost will also increase.

As for the EUV lithography machine that has attracted much attention, Liang Mengsong said that in the current environment, the N+1 and N+2 generation processes will not use the EUV process. After the equipment is ready, the process after N+2 will turn to the EUV lithography process.

From Liang Mengsong’s explanation, the development of SMIC’s 7nm process is similar to that of TSMC. A total of three processes have been developed for the 7nm node, namely low-power N7, high-performance N7P, and N7+ using EUV technology. The first two The EUV lithography machine is not used in the generation process, and the EUV process is only used in the N7+ process, but the number of mask layers is relatively small. The 5nm node size fully utilizes the EUV lithography process, reaching 14 layers of EUV masks.

There is also the time when SMIC’s 7nm-level process came out. In the previous financial report, Liang Mengsong mentioned that the trial production capacity will start at the end of 2020, and the real production will not be until 2021.

Author: Xian Rui

The Links:   CXA-0538-A VBO125-12N07