“Conference phone is an important service of telecom digital switching system, which can realize simultaneous calls between multiple users. In the past, most of the conference phones were implemented with dedicated chips. With the advancement of DSP technology, the use of general-purpose DSPs to realize conference phones has gradually become the preferred solution due to its advantages of large capacity, low cost, and flexible upgrades.
Authors: Yang Zhenxi; Ding Youzhi; Kang Dongming
Conference phone is an important service of telecom digital switching system, which can realize simultaneous calls between multiple users. In the past, most of the conference phones were implemented with dedicated chips. With the advancement of DSP technology, the use of general-purpose DSPs to realize conference phones has gradually become the preferred solution due to its advantages of large capacity, low cost, and flexible upgrades.
TI’s low-power, high-performance DSP TMS320VC5410 has 3 independent data buses and 1 program bus, providing a high degree of parallelism. Its multi-channel buffered serial port McBSP (Multichannel Buffered Serial Port) can easily interface with digital switching systems commonly used in systems. The ST-BUS link, the DMA controller can minimize the occupied time of the CPU inside the DSP, and the on-chip RAM can easily provide the program running space and the McBSP sending and receiving data buffer. Therefore, the DSP is used in this paper to realize the conference phone function.
Algorithm design and implementation
The realization of the conference phone can adopt the maximum output method. This method compares the voice amplitudes of the parties arriving in the same frame. Generally speaking, the speaker has the largest amplitude. After finding the voice with the largest amplitude and the voice with the second largest amplitude, the voice with the second largest amplitude is sent to the the speaker, and the voice with the largest amplitude is sent to other users.
Figure 1 Schematic diagram of the maximum output method conference call
Figure 1 is a schematic diagram of a maximum output method conference phone. The figure takes the four-party conference as an example. The M-th frame PCM encoding of A, B, C, and D is sent to TMS320VC5410 and compared during the M+1-th frame. It is assumed that the voice amplitude of A is the largest, and the voice amplitude of B is the largest. The second largest, so in the M+2 frame, B’s voice is sent to user A, and A’s voice is sent to users B, C, and D. User A hears user B’s voice, and other users hear A’s voice. user’s voice.
Figure 2 DSP data processing flow chart of conference phone
First of all, the DSP starts the transceiver port of McBSP at the same time. When the receiving port of McBSP receives the 8-bit A-law (or m-law) of a certain user time slot, the M-th frame sent by the ST-BUS link corresponds to the 8-bit A-law (or m-law). Encoding as an example) After PCM voice data, first convert it into 13-bit linear code, and then add 3-bit 0 to the right end of the linear code and send it to the receiving register DRR1. This is because TMS320VC5410 is 16-bit and can only The RAM is accessed by 16 bits. In order to improve the efficiency of the algorithm, a linear code is used to compare the voice amplitude in the design. After the linear code conversion is completed, McBSP notifies the receiving DMA controller assigned to it. At this time, the data of DRR1 is ready, and the receiving DMA controller immediately writes the 16-bit data into the receiving buffer according to its corresponding address. In the on-chip RAM of the DSP, we have allocated a data buffer of 2 frames to the receive and transmit ports of the McBSP. For the convenience of software processing, when configuring DMA, when the data buffer allocated to it is half full or full, it sends an interrupt to the CPU in the DSP, so the DMA sends an interrupt to the CPU after receiving the M-th frame of voice data.
When the CPU receives the DMA interrupt, it indicates that the DMA has received the data of all the time slots of the Mth frame. During the M+1th frame, the CPU stores the data in the receiving After taking the absolute value of the voice data of the Mth frame of the user in the data buffer, compare the amplitude and size, find the largest voice and the second largest voice, and write them into the corresponding sending data buffer of the M+2th frame. within the address.
In the M+2th frame, the sending DMA controller reads out the corresponding data from its data buffer in turn and sends them to the sending port of McBSP. The sending port first converts the linear code voice data into A-law voice data, and then completes the PCM Voice data transmission.
TMS320VC5410 has 3 McBSPs and 6 DMAs, all of which can be used for the realization of conference calls. DMA0 “2 can be assigned to the receiving port of McBSP0″2 in sequence, and DMA3″5 can be assigned to the transmitting port of McBSP0″2 in sequence.
On-chip RAM allocation
The TMS320VC5410 has 8K words of 16-bit on-chip dual access RAM (DARAM) and 56K words of 16-bit on-chip single access RAM (SARAM). DARAM consists of 4 blocks, each block is 2K words in size. Each block can be read twice or read and written once in the same clock cycle, so it is suitable for the message buffer between DSP and Host, so 0080h-1FFFh of the data space is mapped to DARAM. SARAM consists of 7 blocks, each block is 8K words in size. SARAM can read one block and write another block in the same clock cycle, so it is suitable for running program area and data area, 2000h of program space? FFFh is mapped to SARAM, and 8000hFFFFh of the data space is mapped to SARAM. The allocation of on-chip RAM is shown in Figure 3, and the specific allocation is as follows:
Figure 3 Schematic diagram of on-chip RAM allocation
1. 0x0080 “0x1FFF, the message buffer of DSP and Host.
2. 0x2000 “0x4FFF, DSP program area, including the .text and .cinit segments of the target file. 0x2000 “0x2080 is the interrupt vector table of the DSP.
3. 0x5000”0x7FFF, DSP data area, including .bss and .stack segments of DSP files.
4. 0x8000 “0x803F, DMA0 buffer, used for McBSP0 reception.
5. 0x8040”0x807F, DMA1 buffer, used for McBSP1 reception.
6. 0x8080 “0x80BF, DMA2 buffer, used for McBSP2 reception.
7. 0x80C0”0x80FF, DMA3 buffer, used for McBSP0 transmission.
8. 0x8100 “0x813F, DMA4 buffer, used for McBSP1 transmission.
9. 0x8140”0x817F, DMA5 buffer, used for McBSP2 transmission.
Configuration of McBSP
McBSP supports 2M and 8M ST-BUS link, here we take 2.048M ST-BUS link with 4.096M input clock as an example, see Figure 4 ST-BUS link schematic diagram. The configuration of McBSP mainly involves the following four registers.
Figure 4 Schematic diagram of ST-BUS link
1. Pin Control Register (PCR)
CLK(R/X)M = 1, the internal transceiver clock CLK(R/X) is generated by the internal sampling rate generator; FS(R/X)P = 1, frame synchronization is active low.
2. Receive/Transmit Control Register (RCR/XCR)
(RX) PHASE = 0, single-phase frame; (R/X) FRLEN1 = 11111, 32 words per frame; (R/X) WDLEN1 = 0, word width 8-bit; (R/X) COMPAND = 11, Receive/transmit data using A-law companding; (R/X)DATDLY = 0, no data delay.
3. Sample Rate Generation Register (SRGR)
CLKGDV = 1, the frequency of the receive/transmit clock CLK (R/X) is 1/2 of CLKS;
GSYNC = 1, external receive frame sync FSR sync CLKG; CLKSP = 1, CLKS
The falling edge generates CLKG of the sample rate generator, which in turn generates CLK(R/X); CLKSM = 1, the external clock CLKS drives the sample rate generator.
4. Multi-Channel Control Registers (MCR1, 2)
RMCM = 0, receive all time slots enabled. XMCM=00, all time slots are enabled.
DMA0 “2 is sequentially assigned to McBSP0″2 reception, and DMA3 “5 is sequentially assigned to McBSP0″2 transmission. The specific configuration is described as follows:
1. DMA Source Address Register (DMSRC)
The DMSRC receiving the DMA stores the address of the DRR of its corresponding McBSP;
The DMSRC that sends the DMA stores the first address of its corresponding data buffer.
2. DMA Destination Address Register (DMDST)
The DMDST receiving DMA stores the first address of its corresponding data buffer;
The DMDST of the sending DMA stores the address of the DXR of its corresponding McBSP.
3. DMA Channel Unit Count Register (DMCTR)
The value of DMCTR sets the size of the DMA data buffer, which is taken as 0x40, that is, the number of user time slots contained in two data frames.
4. DMA Sync Event and Frame Count Register (DMSFC)
DSYN[3:0]=0001, the synchronization event is the receive event REVT0 of McBSP0;
DBLW = 0, single word mode, each item is 16 bits.
5. DMA Transfer Mode Control Register (DMMCR)
AUTOINIT = 0, disable automatic initialization; DINM = 1 of DMA0, IMOD = 1, interrupt is generated when the DMA buffer is half full and full;
DIMM=0 for DMA 1″5, IMOD=X, no DMA interrupt is generated;
CTMOD = 1, DMA works in ABU mode;
SIND=000 of DMA0″2, the source address of the receiving DMA is unchanged;
DMA3 “5’s SIND=001, the sending DMA is taken as the source address increment;
DMS = 01, the DMA source address space is the data space;
DIND=000 of DMA0″2, the receiving DMA is taken as the destination address increment;
DMA3 “5’s DIND=001, send DMA to take the destination address unchanged;
DMD = 01, the DMA destination address space is the data space.
The conference call requires that the voice processing of all conference users must be completed in the DMA interrupt service routine generated by each frame. We take TMS320VC5410 with an operation speed of 100MIPS as an example. The time of one instruction cycle of this DSP is 10ns, so the number of instructions that can be processed in one frame of ST-BUS within 125ms is 125ms/10ns=12500. Since all users participate in the same conference and the voice amplitude increases according to the number of time slots, the processing capacity of the DSP is the largest, so we calculate the processing capacity according to the above conditions. Assuming that when a conference is initiated, the number of users who can participate at the same time is x, then there is the following inequality:
Among them, 254 is the number of common instruction cycles of the interrupt service routine, and 26 is the number of instruction cycles corresponding to each user.
It is calculated from the above formula that x≤471, and the three McBSP links can handle 3×32=96 users (2M ST-BUS link) or 3×128=384 users (8M ST-BUS link) at the same time, so The maximum number of users of the conference phone is ultimately determined by McBSP, that is, 96 users are supported when using a 2M ST-BUS link, and 384 users are supported when using an 8M ST-BUS link.
The use of assembly language code is efficient and the program execution speed is fast. The above algorithm DMA interrupt service routine is implemented in assembly language, and practice has proved that the algorithm is efficient.
The conference phone solution based on TMS320VC5410 introduced in this paper has been successfully applied in the MSC of the CDMA system, and the actual operation on the Internet has fully verified that the solution has the characteristics of large capacity and high performance and price ratio.
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