Detailed Xilinx Multimode Radio Target Design Platform

Numerous industry standards, form factors, frequencies and spectrum ownership are driving the need for increased flexibility in commercial wireless. Xilinx® Multimode Wireless Target Design Platform This is for the needs of high-throughput, signal-processing-intensive systems with domain-optimized FPGAs, IP building blocks, design tools, reference designs, and development boards. Single-chip digital radios can be designed to support multiple standards, greatly simplifying the supply chain and enabling original equipment manufacturers (OEMs) to respond quickly to network provider requirements.

Reduce CAPEX and OPEX through high transmission efficiency

The typical transmission efficiency of the 3G wireless interface of the LDMOS1 power amplifier is between 8% and 15%. The latest generation of power amplifiers and Xilinx Crest Factor Reduction (CFR) and Digital Pre-Distortion (DFD) LogiCORE™ IP utilize advanced digital algorithms, efficiency can increase it to 35% to 45%. This represents annual operating expenditure (OpEx2) cost savings of as much as $20 million for a typical network of 10,000 base stations. By using smaller transistors in the power amplifier, capital expenditure (CapEx3) can also be reduced, and the same transmit power rating can be used on the antenna.

Integration is the key to reducing power and cost and improving reliability

Replacing multiple ASSPs with a single FPGA enables the smallest digital PCB footprint. Xilinx’s FPGAs combine rich DSP and logic circuit resources to efficiently implement digital up-conversion (DUC), digital down-conversion (DUC), digital down-conversion (DUC), and multi-gigabit transmitters (MGT) capable of CPRI, OBSAI or JESD204A connectivity. Transform (DDC), CFR and DPD algorithms. The low-power, high-performance fabric of Xilinx FPGAs provides class-leading power performance and the lowest overall board cost.

Example: 2 transmit, 2 receive (2×2) LTE-DFE reference design using DPD LogiCORE IP

Reference Design Features

• DUC/DDC for 5, 10, 15 and 20MHz single carrier and 2×5, 2×10 and 4x5MHz multicarrier options per antenna
• Xilinx CFR, output Peak-to-Average Power Ratio (PAPR) -7dB at Error Vector Magnitude (EVM) 70dB
• Xilinx DPD supports up to 4 transmitters with a single MicroBlaze™ processor engine, which can provide up to 30dB spectral correction performance and over 40% Doherty power amplifier efficiency
• Full OBSAI master-slave PHY supports line speeds up to 6.144Gbps with built-in low-power MGT
• Scalable to 2×4 (2T4R) and 4×4 (4T4R) antenna arrays in combination with Virtex®-6 FPGA package migration

FPGA resource utilization

• Includes all resources marked in the image above, including:
o DAC/ADC interface
o Microprocessor interface
o OBSAI master-slave
o OBSAI Simple Application Layer
o 2 transmit, 2 receive DUC/DDC/CFR with the following carrier configurations implemented using the Xilinx LTE-DFE reference design, and Xilinx DPD LogiCORE IP

Multimode Wireless Demonstration Platform

The design of radio frequency subsystems can be closely related to their application environment. This is especially evident for complex algorithms such as digital predistortion, where it is difficult to model analog circuit effects such as thermal and reactive transistor memory and characteristics of analog signal links.

Xilinx is already working with AnalogDevices to manufacture a high-performance multimode wireless demonstration platform that can demonstrate DPD solutions for third-party power amplifiers at various frequencies and any wireless interface. The XilinxML605 board and Analog Devices’ mixed-signal digital predistortion (MSDPD) board are connected via the FMC header on both boards. Advanced signal processing applications with DUC, DDC, CFR and DPD functions are implemented on the XilinxML605, taking full advantage of the high-performance data converters and RF signal chain on the Analog Devices MSDPD board.


Xilinx ML605 board

• SFP connectors support OBSAI and CPRI connectivity requirements
• Virtex-6 LX240T FPGA enables users to develop complex DUC/DDC, CFR and DPD algorithms for any waveform
• For complete specifications, visit:

Analog Devices’ MSDPD board

• Support transmission bandwidth over 20MHz
• Configurable on assembly for 800MHz – 2.7GHz RF frequencies
• 20dB RF output power adjustment, 10-bit resolution
• +10dBm RF output power
• Meets demanding MC-GSM performance requirements (with AD9122)
• Data converter footprint compatible with lower specification models

Summary of Existing Xilinx Wireless Reference Designs

Existing Xilinx Wireless Logicore IP Summary

For more information on Xilinx wireless solutions, please visit

The Links:   7MBR35SB120-50 AA121XH03