“Combining the advantages of digital frequency synthesizers (DDs) and integrated phase-locked loops (PLL), developed and designed a high-resolution, low-spurious, wide-band frequency synthesizer composed of DDS chip AD9954 and integrated phase-locked chip ADF4113 , And analyzed and simulated the frequency synthesizer. From the simulation and test results, the frequency synthesizer has reached the design goal. The output frequency range of this frequency synthesizer is 594-999 MHz, the frequency step is 5 Hz, and the phase noise is -91 dBc/.
Authors: Zhu Qingfu, Xi Youbao, Dong Lifang
Combining the advantages of digital frequency synthesizers (DDs) and integrated phase-locked loops (PLL), developed and designed a high-resolution, low-spurious, wide-band frequency synthesizer composed of DDS chip AD9954 and integrated phase-locked chip ADF4113 , And analyzed and simulated the frequency synthesizer. From the simulation and test results, the frequency synthesizer has reached the design goal. The output frequency range of this frequency synthesizer is 594-999 MHz, the frequency step is 5 Hz, and the phase noise is -91 dBc/.
The reference signal of DDS is produced by crystal oscillator, and its frequency is fref. The frequency of the signal output by DDS is fDDS, and the frequency value is controlled by the frequency control word (FTW). The reference signal of the phase-locked loop (PLL) is driven by the output signal of the DDS. The output frequency of the VCO is output by the charge pump (CP) of the PLL chip and controlled after passing through the low-pass filter (LPF). The output signal of the frequency synthesizer is the output signal of the VCO. The frequency synthesizer provides a control signal through a single-chip microcomputer to change the frequency division ratio of FTW and PLL in DDS.
The relationship between VCO output signal frequency and DDS output signal frequency is:
In the structure shown in Figure 1, because the DDS module has a higher frequency resolution, it can be seen from equation (3) that the output signal theoretically has a higher frequency resolution than the traditional structure. The crystal oscillator frequency is 400 MHz in the design, and the PLL frequency division ratio is 27. From the calculation of formula (3), it can be known that the frequency source can achieve a frequency resolution of 5 Hz. Among them, the output frequency of DDS is 22-37 MHz, so the output frequency range of the system is 594-999 MHz, which meets the design requirements.
1.2 Circuit realization
For the DDS module, the AD9954 chip is used to generate the low-frequency reference signal. AD9954 is ADI’s latest AgiIeRF synthesizer, with a 32-bit frequency control word. At a clock frequency of 400 MHz, the output frequency resolution can reach about 4.7×10-5 Hz, with a 14-bit programmable phase shift unit. The chip adopts advanced: DDS technology, internal integrated 14-bit high-performance DAC. The DAC has excellent dynamic performance, and the phase noise is better than -120 dBc/.
The PLL module is particularly important in this design structure. ADF4113 phase-locked loop chip is used here. The digital phase-locked frequency synthesizer ADF4113 developed by ADI has a maximum operating frequency of 4 GHz and is mainly used in the field of wireless radio to form a digital phase-locked loop to lock a certain frequency. The internal resources of the circuit mainly include programmable analog frequency dividers: 8/9, 16/17, 3z/33, 64/65; programmable 14-bit reference frequency divider; programmable radio frequency signal divider; 3-wire serial bus interface; analog and digital lock status detection function. The highest phase discrimination frequency of this chip reaches 55 MHz, and the bottom noise of the chip is -171 dBc/.
2 Circuit analysis and simulation
In order to analyze and estimate the performance of the proposed frequency synthesizer, ADISimPLL software is used to simulate the phase noise of the scheme. The simulation results are shown in Figure 4 and Figure 5. The phase noise simulation graph and the lock time graph with a frequency of 810 MHz and a loop bandwidth of 120 kHz are given here. As can be seen from the figure, this scheme meets the requirements of the design goal.
3 Experiment and measurement results
In order to verify the performance of the frequency synthesizer given in the article, Agi-lent E4401B is used to measure the phase noise and spurs of the frequency sweep source. The measurement results are shown in Figure 6 to Figure 8. 594″999 MHz contains many frequency points. During the test, a series of representative points were selected for measurement. Due to space limitations, the measurement results of phase noise and spurious at the 810 MHz frequency point are given here. As can be seen from the figure, phase noise It is -92 dBc/.
A frequency synthesizer using DDS to excite PLL is introduced, which effectively overcomes the shortcomings of low DDS output frequency and low PLL frequency resolution in broadband systems. Complementing each other’s strengths to achieve frequency synthesis, achieving an effect that is difficult to achieve with a single technology.
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