Tsinghua Unigroup released GDDR6 controller and physical interface IP: 12nm process, speed up to 16Gbps

On November 6th, Tsinghua Unigroup officially released the GDDR6 memory controller and physical interface IP (GDDR6 MC) based on the GF 12nm low-power process (GF 12LP) at the China Global Technology Conference held by GLOBALFOUNDRIES. /PHY IP).

The official said that compared with the existing solutions, the new solution has obvious improvements in chip power consumption, area and cost, and can meet the growing demand in hot areas such as artificial intelligence (AI) and computing applications.

It is understood that Xi’an Tsinghua Unigroup’s GDDR6 MC/PHY IP includes a configurable memory controller (MC) that is fully compliant with DFI3.1 and AMBA AXI4.0 standards and allows design engineers to generate GDDR6 with optimized latency and bandwidth Controllers to meet the requirements of high-performance applications such as graphics cards, game consoles, and AI computing. The IP is optimized for power consumption and performance. Xi’an Unigroup’s GDDR6 physical interface (PHY) provides data rates up to 12Gbps/13Gbps/14Gbps/16Gbps, and is compatible with JEDEC250 and DFI3.1 standards. The physical interface (PHY) section also embeds a high-performance phase-locked loop to meet stringent timing specifications. Integrated with mainstream GDDR6 memory chips, and verified by tape-out testing, the performance of this IP meets design specifications at 12Gbps/14Gbps/16Gbps data rates. And when the data rate is 16Gbps, the average maximum power consumption of each DQ is less than 4mW/Gbps.

At present, Tsinghua Unigroup’s GDDR6 MC/PHY IP has been launched on GF’s 12LP process platform.


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